Your question about Siemens S30810-Q2250-X100 DP4L

The DP4L (Data Processor 486 with LAN Node) is based on the DP486 board. As far as possible, the implementation is compatible to the DM3L module. Following features have been adapted:

• As CPU only an intel i486SX-33 microprocessor is used.
• The EPROM and FLASH EPROM memory size has been increased to 256 Kbytes in both cases; the memory can be deactivated if required.
• A LAN node is implemented.
• Monitoring and testing has been improved.
• The Multibus lost its multi master capability, the timeout delay is fixed.
• The MAC interface has been omitted, the mutual partner signaling is unbalanced.
• Der Backplanestecker ist ein SIPAC-Stecker. The backplane connector changed to SIPAC.
• The front panel button MON has been replaced by TST.

The i486SX has access to an on-board processor bus. The local memory and the LAN controller together with their I/O ports as well as an on-board peripheral bus connect directly to this processor bus. The peripheral bus connects the EPROM and FLASH memory, the peripheral components (timer, interrupt controller, configuration ports), the I/O subsystem (V.24 controller, human and partner IF) and the system bus to the processor bus.

One asynchronous V.24 interface provides access for monitoring. Logic interfacing to an optional partner DP4L is implemented. The system bus interface allows addressing of off-board I/O ports and memory. The LAN node forms a high speed interface to other modules.